Processing of silicon wafers is commonplace in the manufacture of modern microelectronics devices. Such processing, including plasma processing and ion implantation may be performed at low pressures, wherein RF or microwave plasmas, or high-power particle beams are delivered to the wafer, therein producing high temperatures at the wafer during processing. Such high temperatures, however, can have deleterious effects on the wafer.
Wafer temperature control in semiconductor processing has utilized electrostatic chucks (ESCs) for some time. A typical single-polar ESC is illustrated in FIG. 1, wherein the ESC 10 holds the wafer 20 in place by electrostatic force. The wafer 20 is separated from an electrode 30 by an insulating layer 40. A voltage (e.g., illustrated as a+) is applied to the electrode 30 by a voltage source 50. The voltage applied to the electrode produces an electrostatic field (e.g., illustrated as a“−”) at the wafer 20 which induces an equal and opposite charge (e.g., illustrated as a+) on the wafer 20. The electrostatic field on the wafer 20 produces an electrostatic force between the wafer and the ESC 10. Consequently, the electrostatic force holds the wafer 20 against the insulating layer 40.
Cooling of the wafer 20 can occur through contact conductivity between the wafer and a contact surface 60 of the insulating layer 40, wherein the insulating layer may be cooled by cooling water. Conventionally, the cooling of the wafer 20 generally increases with the voltage applied to the ESC. Significantly high voltages, however, can have deleterious effects on the wafer (e.g., a cause of particle generation), and may further have costly power supply and consumption considerations, along with increased failure rates.
In vacuum environments, conventional ESCs utilize a cooling gas between the wafer 20 and the insulating layer 40, wherein a contact surface 60 of the insulating layer 40 comprises a region for the cooling gas to reside. However, conventionally machining an insulating layer 40 comprised of a ceramic typically has several drawbacks, both in terms of precision, as well as potential particulate concerns caused by the ceramic layer during wafer processing.
A thickness of the insulating layer 40 between the clamp electrode 30 and the wafer 20 affects a local clamping force, thereby impacting thermal uniformity across the wafer. Conventional manufacturing methods provide poor control over this dimension, however. Non-uniformities in the insulating layer 40 and the physical gap between the clamp 10 and wafer 20 produce potentially large spatial variations in clamping pressure, making precise temperature control difficult. Models and measurements indicate that, conventionally, an average gap width typically varies depending on the surface and clamping conditions. This relatively large and uncontrollable gap width across the wafer typically results in a lower cooling capability and a non-uniform temperature across the wafer.
When using an ESC, the entire back side of the wafer can be held tightly to the surface of the ESC. Particulates are created when two hard surfaces are held together in this manner due to the crushing of micro-features of the surfaces. Therefore, the interface between the surfaces of the ESC and wafer becomes a source for particulate generation.
Thus, there is a need in the art for an electrostatic chuck that provides a clamping surface which is operable to significantly limit particulate contamination during wafer processing.